New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Saturday, August 27, 2011
FPGA design from scratch. Part 54
Using the ISE Simulator

ISE Simulator ISim is the only RTL simulator available to us. Is it as good as the Mentor ModelSim and the Cadence IUS? Let's find out.

We will start out by downloading the
ISim User Guide.

Here is the
on-line help and here is an ISim In-Depth Tutorial.

Overview of ISim

The Xilinx® ISE Simulator (ISim) is a Hardware Description Language (HDL) simulator that enables us to perform functional (behavioral) and timing simulations for VHDL, Verilog and mixed-language designs.
This ISE Simulator environment is comprised of the following key elements:
  • vhpcomp (VHDL parser)
  • vlogcomp (Verilog parser)
  • fuse (HDL elaborator and linker)
  • Simulation executable
  • isimgui (Isim graphical user interface)
vhpcomp, vlogcomp

vhpcomp and vlogcomp parse and compile VHDL and Verilog source files respectively. The parsed dump generated by the parsers is used by fuse to generate object code and link object code with simulation kernel library to create a simulation executable.


The fuse command is the Hardware Description Language (HDL) elaborator and linker used by ISim. fuse effects static elaboration on the design given the top design units and then compiles the design units to object code. The design unit object files are then linked together to create a simulation executable. The fuse command can automatically invoke vlogcomp and vhpcomp for each VHDL or Verilog source code in a project file (.prj), allowing you to compile sources "on-the-fly".

Simulation executable

The Simulation Executable is generated by the fuse command. To run the simulation of a design in ISim, the generated simulation executable needs to be invoked. When ISim is run inside the ISE Project Navigator interface, ISE takes care of invoking the generated simulation executable. A command-line user needs to explicitly invoke the generated simulation executable to effect simulation. The simulation executable effects event-driven simulation and has rich support for driving and probing simulation using Tcl.


isimgui.exe (isimgui on Linux) is the ISim Graphical User Interface. It contains the wave window, toolbars, panels, and the status bar. In the main window, you can view the simulation-visible parts of the design, add and view signals in the wave window, utilize ISim commands to run simulation, examine the design, and debug as necessary.

ISim Operating Modes

The simulator can be used in three different operating modes:
  • Graphical User Interface Mode
  • Interactive Command Line Mode
  • Batch Run Mode
The ISim simulator can run inside the ISE Project Navigator or as a stand-alone tool. We will use it as a stand-alone simulator and I will also add support for ISim to the Mongoose verification environment.

Batch Run Mode

I will start by describing the batch run mode which I find the fastest and best way to run simulations.

Simulating our design

Here is what our design looks like. For more information see 

Simulation steps

The basic steps for simulating our design in ISim are as follows:
  1. Gathering files and mapping libraries
  2. Parsing and elaborating the design and test bench
  3. Simulating the design
  4. Examining the design
  5. Debugging the design
Gathering files and mapping libraries

We will start by creating a project file (ETC_design.prj) where we put all the Verilog design files:

verilog design $ETC_DESIGN/etc_testgen.v
verilog design $ETC_DESIGN/etc_tdo_record.v
verilog design $ETC_DESIGN/etc_tckgen.v
verilog design $ETC_DESIGN/etc_regs.v
verilog design $ETC_DESIGN/etc_dual_port_mem.v
verilog design $ETC_DESIGN/etc_dual_port_1024x32.v
verilog design $ETC_DESIGN/etc_config.v
verilog design $ETC_DESIGN/etc.v

The environment variable ETC_DESIGN points to the design directory.

Each line in the project file consists of three entries. Like this:

verilog/vhdl <library name> {<file_name_1.v|.vhd}

  • verilog/vhdl indicates that the source is a Verilog or VHDL file. Include either verilog or vhdl
  • <library name> indicates the library that a particular source on the given line should be compiled.
  • <file name> is the source file. More than one file can be specified.
Compiling the design

The following command is used to compile and elaborate the design:

fuse design.ETC -prj project/ETC_design.prj

Fore more information about the fuse command see the ISim user guide.

Compiling the testbench

We will start by creating a new project file (ETC_test.prj)  containing the verilog test bench:

verilog work $ETC_VERIFICATION/testbench/ETC_testbench.tb

The following command is used to compile and elaborate the testbench together with the design:

fuse ETC_TEST -prj project/ETC_test.prj -L design -o test.exe

The output from the compilation is an executable c-program (test.exe).

Run a simulation

Use the following command to start the simulation:

./test.exe -tclbatch tcl/run_test

The tcl command file (run_test) looks like this:

wave log -r /      (save all signals to the waveform plot file)
run all            (run simulation to finish)

Debugging the design

The best way to debug our design is to use a waveform viewer and look at the waveform plot file generated during the simulation phase. The waveform file is stored in the verification directory and the default name is isim.wdb. Use the following command to open the file in the ISim waveform viewer:

isimgui -view isim.wdb

Here is what the display looks like.

Using a wave configuration file

The default wave configuration file (Default.wcfg) will display all signals in the design. We can select the signals we would like to look at and save it to new wave configuration file. Select Save As from the File menu:

Use this command to open the waveform viewer and the saved wcfg file:

isimgui -view isim.wdb -open etc.wcfg &

Ignore the following error message:

The verification file tree

Running a simulation in ISE

Let us repeat the same thing but this time we will use the ISE project Navigator. We will start by reading in the design files and the test bench files. Right-click the ETC_SYSTEM entry in the hierarchy browser and select Add Source.

Adding the verilog design files.

Adding the test bench file.

Here are all the files that have been added. The include files will be added automatically if the relative path names are pointing to the right files.

Click the Simulation radio button to select the simulation operating mode.

When we select simulation mode the Process window looks like this:

Compiling the verilog code

Right-click the <Behavioral Check Syntax> entry and select <Rerun All>. The following command is executed:

vlogcomp -work isim_temp -intstyle ise -prj /home/svan/projects/ETC_SYSTEM/ETC_TEST_stx_beh.prj

Running a simulation

Right-click the <Simulate Behavioral Model> entry and select <Rerun All>. The following compilation command is executed:

fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/svan/projects/ETC_SYSTEM/ETC_TEST_isim_beh.exe -prj /home/svan/projects/ETC_SYSTEM/ETC_TEST_beh.prj work.ETC_TEST work.glbl {}

When the compilation has finished the simulation will automatically start using thefollowing command:

/home/svan/projects/ETC_SYSTEM/ETC_TEST_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd  -wdb "/home/svan/projects/ETC_SYSTEM/ETC_TEST_isim_beh.wdb"

The waveform window is displayed and the simulation will run for 1000ns.

To finish the simulation select Run All from the Simulation menu.

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