New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Sunday, September 18, 2011
FPGA design from scratch. Part 65
Putting together an embedded system

We are ready to start assembling our own embedded system. We will follow the procedures in "Introduction to MicroBlaze Hardware Development" labs found in the Avnet Design Resource Center.

Xilinx Platform Studio XPS

We will build the system from ground up using the Xilinx Platform Studio. For more information see and the Xilinx documentation.

Getting help

Every time we run into problems using Xilinx Platfrom Studio we can get help from the Help menu. Select Help->Help Topics to display this page.

EDK Reference Manual

The Embedded System Tools Reference Manual can be found

Starting XPS

--> xps &

We use the Base System Builder wizard to help us put together the system.

This time we will build an
AXI based system.

We select the Avnet Spartan-6 LX9 MicroBoard and a single MicroBlaze processor system optimized for area.

Adding and removing peripherals.

Remove DCDE913_I2C core
Remove DIP_Switch_4Bits core
Remove Ethernet_Lite core

Add AXI_timer core and enable interrupt. The interrup controller will be added automatically when the use interrupt option is selected. Set instruction and data cache sizes to 2KB.

Click finish.

Here is our embedded system displayed in the XPS System Assembly window. The Base System Builder wizard created all the files needed to get started with an embedded MicroBlaze system. The System Assembly view shows each peripheral used and the connections between the peripherals when the Bus Interface tab is selected.

The Project window provides information on the project options used, gives access to the main project files, and log files. The main project files are:
  • MHS file. The Microprocessor Hardware Specification file contains the hardware specification of the entire system. The MHS file contains the bus architecture, list of peripherals, connectivity for the system, interrupt request priorities, and address space.
  • UCF file. The User Constraints File contains the timing and placement constraints for the FPGA.

View design summary

Select Project->View Design Summary to get a Device Utilization Summary.

Generate a block diagram

From the project Menu select <Generate Block Diagram Image>. The image is saved in the blockdiagram directory.

Generate a design report

To generate a datasheet of the system select Project->Generate and View Design report. The file generated is in html format and is displayed in the web browser. The file is stored in the subdirectory Report.

The system file tree

Here is the file tree displaying all the files generated in this process.

Synthesise the design

To synthesise the design and generate a netlist, select Hardware->Generate Netlist

Generate the bitstream

To generate the bit stream file used to program the FPGA, select Hardware->Generate Bitstream

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