New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

If you want to be updated on this weblog Enter your email here:

rss feed

Tuesday, September 20, 2011
FPGA design from scratch. Part 67
Adding an EDK IP to an embedded system

This tutorial demonstrates how to add and modify peripherals to an existing MicroBlaze system using Xilinx Platform Studio (XPS). The system from the previous tutorial will be used as the starting point. We will follow the instructions from the "Introduction to MicroBlaze Hardware Development Lab 2". The tutorial will show:
  • How to add an EDK peripheral
  • How to connect to the existing system
  • How to modify the peripheral options
  • How to add constraints for the new peripheral

This is what our embedded system looks like. We will add a General Purpose IO (GPIO) core to make use of the DIP switches on the board.

Skipping ISE

We will do all the hardware design implementation in XPS and all software writing in SDK. From now on we skip ISE to make things easier.

Finding and adding an EDK IP

In XPS click the IP Catalog tab to display all available IPs provided by Xilinx. Open up the General Purpose IO and select AXI General Purpose IO 1.01a. Right-click the entry and chose Add IP.

The peripheral configuration window will open automatically. Select Channel 1 and change the GPIO Data Channel Width from 32 to 4. Change Channel 1 is Input Only from 0 to 1.

The peripheral is connect to the MicroBlaze core.

In the System Assembly click on the axi_gpio_0 and rename it to DIP_Switches.

Generate addresses

Click on the Address tab to display this window. The addresses view shows the address space for all peripherals. The Lock box prevents the address for that peripheral from being changed when generating new addresses.

Click on the Generate Addresses button   to generate the address range for the new GPIO peripheral.

GPIO interface

To view the datasheet for the GPIO interface right-click the AXI General Purpose IO entry in the IP Catalog and select <View PDF Datasheet>. Here is the schematics taken from the datasheet.

Connecting ports

Click on the ports tab. The Ports view shows the internal connections between the peripherals as well as the external ports. Expand the DIP_Switches. It will show the connections available for the peripheral.

  1. Expand the (IO_IF) gpio_O selection.
  2. Select the GPIO_IO_I since the DIP switches are only inputs.
  3. Click on <No Connection> drop-down list in the Net column.
  4. Select <Make External> to add the port to the external port list.
  5. Select GPIO_IO net and set <No Connection>.

Modifying the UCF file

The User Constraint File (UCF) holds design constraints for external input and output pins in our design. It was generated automatically when we generated our hardware design the first time. After adding an IP core manually we have to manually enter constraints for new external ports. The ucf file can be found in the project sub directory called data.

To edit the UCF file double-click the UCF File entry in the Project Files window and add the following lines:

These pins are hardwired to the DIP switches.

Generate new netlist and bitstream

Select Hardware->Generate Netlist to generate a new netlist.
Select hardware->Generate Bitstream to generate a new bitstream.


Adding a standard Xilinx IP core is a simple task if you know how to do it.

Top Previous Next

Posted at 09:28 by


Leave a Comment:


Homepage (optional)


Previous Entry Home Next Entry