New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Saturday, October 01, 2011
FPGA design from scratch. Part 71


Embedded ChipScope Debugging

This tutorial demonstrates how to debug and investigate AXI transactions in the embedded system using ChipScope Pro. The tutorial will show:

  • How to add a ChipScope AXI Bus Monitor to our embedded processor
  • Generate a FPGA Bitstream with embedded ChipScope core and SDK software application.
  • How to view and interpret AXI Bus transactions using ChipScope Analyzer.

ChipScope Pro Tools Overview

As the density of FPGA devices increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope Pro tools integrate key logic analyzer and other test and measurement hardware components with the target design inside the supported Xilinx FPGA devices. The tools communicate with these components and provide the designer with a robust logic analyzer solution.

The ChipScope Pro Serial I/O Toolkit provides features and capabilities specific to the exploration and debug of designs that use the high-speed serial transceiver I/O capability of Xilinx FPGAs. The IBERT (internal bit error ratio tester) core and related software provides access to the high-speed serial transceivers and perform bit error ratio analysis on channels composed of these transceivers. The IBERT core supports the high-speed serial transceivers found in the Xilinx KintexTM-7, Virtex®-5, Virtex-6, and Spartan®-6 FPGA devices listed in the ISE Design Suite Product Table. For more information see the ChipScope Documents page.

Adding the ChipScope AXI Monitor Core

The AXI Monitor is a wrapper for the ChipScope Integrated Locig Analyzer (ILA) core. This monitor creates a specific ILA for monitoring AXI signals by creating trigger groups designed to be useful for debugging of the AXI bus.

In XPS open the Debug Configuration Wizard by selecting <Debug->Debug Configuration>.

Select <Monitor Hardware Signals> the click <Add ChipScope Peripheral>.

Click OK to exit. In the next window we will select which AXI interfaces we want to debug. We will probe the interface between MicroBlaze and the AXI interconnect block (microblaze_0.M_AXI_DP).

Click OK to finish the debug setup. Here is the result.

Go to Project -> Export Hardware Design to SDK and select Export Only. A new netlist and bitstream will be generated. Oops what happened. This error message tells us that the new design didn't fit in the FPGA.

Making the design smaller

We will delete the SPI_FLASH interface which we don't need right now. But before we do that we are going to keep a copy of the original design which can be reused later on. Copy file LX9_AXI_system.mhs to LX9_AXI_system_orig.mhs

We must remove some of the pins not connected anymore.

This time the bitstream generation runs without problem.

Configure the FPGA in SDK

We configure the FPGA and start the application program to make sure everything still works. We can see that LEDs intensity changes when we set the DIP switches to new values.

Analyzing the design with ChipScope Pro Analyzer

Use the command analyzer to start ChipScope.

--> analyzer &

Connecting ChipScope Pro Analyzer to target

Select Diligent USB JTAG Cable from the JTAG Chain menu. This window will pop up.

Click OK to connect. The device XC6SL9 is found and the JTAG chain is connected.

Here is the console printout.

Adding AXI signal names

We need to add the CDC file to attach names to the ChipScope signals. From the FIle menu choose Import and click Select New File. Navigate to ChipScope AXI Monitor IP directory and find the cdc file.

The Signals display window will show all signals available.

Capture waveform data

The program is running and we are ready to trigger and sample waveform data. Double_click Trigger Setup and Waveform entries to display the windows (if not already displayed).

Click the Trigger Anything (T!) button to fill the waveform window with data. 

Here is the result.

Setting a trigger

This time we will trigger the waveform data capture when certain conditions occur. Open the Trigger Setup. Configure the Trigger as follows.

  • In the M0:ARADDR row, change the radix to hex
  • Set the value to 4002_0000
  • Expand M7:RDATAACONTROL, change MON_AXI_RVALID to 1
  • Set position to 512 (in the middle of the waveform window display)
  • Double-click the Trigger Condition Equation, enable M0 amd M7. Click OK

This what the trigger setup looks like.

Click the Trigger button . The trigger should be centered on a valid read transacation (RVALID = 1) from address 0x4002_0000. The value in MON_AXI_RDATA should represent the status of the DIP switches on the board.

Top Previous Next

Posted at 14:57 by

November 2, 2011   06:28 PM PDT
Your blog is just fantastic and the amount of information it has is mind blowing...Keep continuing the great work Sven.
October 5, 2011   03:31 PM PDT
Hi Lars Johan,

I will try to install PetaLinux on this board. According to Avnet it can be done.


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