New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, October 18, 2011
FPGA design from scratch. Part 72
Running Linux on the LX9 MicroBoard

This tutorial will show how to build and install a Linux OS on our MicroBlaze processor system. We will take a look at some of the Linux distributions available to us and choose the one we think is the best for our purpose. For more information about Linux in Xilinx products see Xilinx Wiki. 

Here are some candidates:

Choosing PetaLinux

After taking a closer look at all the candidates I have decide to go for PetaLinux. PetaLogix has a long experience in using the MicroBlaze processor and has build many Linux distributions for this processor. PetaLinux is not a free distribution, but after talking to John Williams, the founder of PetaLogix he promised me a free evalution license for trying the PetaLinux SDK.

While we are waiting for the license, here are some documents we can study to get a better understanding of the process to build and install a Linux OS.

Building the hardware platform

We will follow the Ting Cao's blog and his advises on how to make the design fit in the Spartan-6 FPGA on the LX MicroBoard. Let's go through the whole design flow once more.

We will start a new project and use the BSB wizard to build our system.

->xps &

We select the Avnet Spartan-6 LX9 MicroBoard and let the reference clock run at 66MHz.  We will optimize for area, our biggest concern.

  • Set processor frequency to 66MHz
  • Set local memory size to 8KB
  • Set cache sizes to 8KB
  • Remove CDCE913_I2C and DIP_Switches_4bits peripherals
  • Add axi_timer peripheral
  • Enable interrupts for all peripherals
  • Change the baud rate to 115200 for the uart

Here is the generated hardware platform and here is the corresponding mhs file.

Configuring the MicroBlaze soft processor

Right-click the micro_blaze0 entry and select Configure IP. For more information about MicroBlaze see part 60.

Select <Linux with MMU> and the click the Advanced button. Here are the settings for the General tab.

Here are the settings for the Exceptions tab.

Here are the settings for the Cache tab.

  • Instruction cache size : 8KB
  • Data cache size: 8KB
  • Base Address: 0x8000_0000
  • High Address: 0x83ff_ffff

Here are the settings for the MMU tab.

Here are the settings for the Debug tab.

Here are the settings for the PVR tab.

Interconnect Settings for BUSIF tab.

The Buses tab. This finalizes the MicroBlaze configuration.

Configure the debug_module

Right-click the debug_module entry and select Configure IP. We will disable the JTAG UART bus interface to save area.

Synthesize the design

In XPS select Hardware->Generate Netlist to synthesize the design. Here is the result from the syntesis (estimated values).

Place and route the design

In XPS select Hardware->Generate Bitstream to place and route the design and find out if it will fit in the Spartan-6 FPGA. Here is the result. It will fit.

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