New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, October 26, 2010
Designing with an Actel FPGA. Part 1


There are other players in the FPGA arena. Actel is one of them. They now belong to Microsemi, a company that has a wide range of products. See their web page for more information.

We will go directly to the FPGAs which takes us to the Actel webpage.

Product description

The product we are going to design has to fit in the Märklin Gauge Z train and has a very low power consumption. It will consist of an FPGA with analog sensors and a radio communication unit.

Z scale (1:220) is one of the smallest commercially available model railway scales with a track gauge of 6.5 mm/0.256 in. Z scale trains operate on 0-10 volts direct current (DC) and offer the same operating characteristics as all other two-rail, direct-current, analog model railways. Z scale locomotives can be retro-fitted with microprocessor based digital decoders for digitally controlled model railways. Model trains, track, structures, and human/animal figures are readily available in European, North American, and Japanese styles from a variety of manufacturers.

Selecting an FPGA

Choosing the right FPGA can be a tough decision to make. The deciding factors in our project are:

  • Low power consumption
  • Small physical size
  • Nonvolatile programming
  • Low operating voltage
  • Low speed

It looks like a perfect fit for the Actel IGLOO FPGA family.

The IGLOO family

The Actel IGLOO series of low-power FPGAs includes IGLOO/e, IGLOO nano, and IGLOO PLUS devices—the industry's lowest-power FPGAs. IGLOO devices are reprogrammable, full-featured flash, low-power FPGAs designed to meet the demanding power and area requirements of today's portable and power-conscious electronics. Based on Actel nonvolatile flash technology and single-chip ProASIC®3/E FPGA architecture, the 1.2 V / 1.5 V operating voltage family offers the industry's lowest power consumption, smallest footprint, and competitive prices.

The smallest of them all is IGLOO nano.

FPGA selection

We will use the IGLOO nano AGLN250 in 5x5 mm package which will hopefully fit in the Märklin train. The FPGA comes in a  chip scale package not much larger than the chip itself.

Package data

Here is package data for the CS81 package.

Actel FPGA development software

Libero Integrated Design Environment is Actel's comprehensive software toolset for designing with all Actel FPGAs, including Actel's new SmartFusion family, the world's only FPGA with hard-wired ARM Cortex-M3 and programmable analog.

From design, synthesis and simulation, through floorplanning, place-and-route, timing constraints and analysis, power analysis, and program file generation, Libero IDE manages the entire design flow quickly and efficiently. 

Installing Libero IDE software

Let's go to the download page and download the Linux version of the software.

Click the link Download Libero v9.1 SP3 for Linux.

We will start by downloading and installing Libero IDE v9.1 Software for Linux - Capture

It is almost 1GB of data. It will take some time. Why not have a cup of coffee while we are waiting. When the download has finished unzip the downloaded file and change the permissions to make it executable.

--> gunzip LiberoLU91_Lin.bin.gz

--> chmod 755 LiberoLU91_Lin.bin

Running the installer

Execute the following command to start the Libero IDE installer. Before starting we have to follow the installation instructions given in the page above.

-->cd <download_dir>

--> sudo ./LiberoLU91_Lin.bin

Choose an installation directory.


Choose the install set.

Start the installation.

Installation directory

Here is the directory structure for the Libero IDE installation.

Installing a service pack

We are now ready to install the service pack SP3 on top of the normal installation.

Here are the installation instructions from the READMe file.

To install run : sudo ./

Installation finished

We have finished the Libero IDE installation. The next thing we have to do is obtain a license file from Actel and start a license server on our Linux host. See next part in this tutorial.

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