Designing with an Actel FPGA. Part 5
Using the Libero Integrated Design Environment
We will use Libero IDE to put together our first project from scratch. The VHDL code is already available to us. The design is a Pulse Width Modulator (PVM) that will be used to control the speed of our train.
Here is the Libero IDE User's Guide and here is the Libero IDE Quick Start Guide..
--> libero &
From the Project menu select New Project. It will open the New Project Wizard. Enter a project name and select a destination directory for the project directory (PWM).
Select FPGA family, die and package.
Add files to the project. We will start by adding the VHDL RTL design files.
Completing the New Project Wizard.
When we click the Finish button the new project will be generated and the Project Flow window will be displayed in the Libero Project Manager.