New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


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and ask questions or make comments
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New Horizons
What's new
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
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38000 feet above see level
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Photo Albums
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Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
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d9 Tech Blog
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EDA DesignLine
Eli's tech Blog
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Sunday, November 13, 2011
FPGA design from scratch. Part 79

Configuring the Spartan-6 FPGA


Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3Mb and 33Mb depending on the device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin low (pressing the push button SW4). Several methods and data formats for loading configurations are available. For this to work the configuration data must be stored in the on-board SPI flash. This tutorial will show how to program the SPI flash.

Bit-serial configurations can either be master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the FPGA. The available JTAG pins use boundary-scan protocols to load bit serial configuration data. The bitstream configuration information (download.bit) is generated by the ISE software using a program called BitGen.

The Xilinx ISE PROMGen software takes an FPGA bitstream (.bit) file as input and, with the appropriate options, generates a memory image file for the data array of an SPI serial flash. The output memory image file format is chosen through a PROMGen software command-line option. Typical file formats include Intel Hex (.mcs) and Motorola Hex (.exo).

Note: Throughout this document, the word configuration applies to downloading a bitstream to the FPGA whereas the word programming applies to downloading a flash image to the on-board serial flash.

Internal configuration process

The configuration process typically executes the following sequence:

  • Detects power-up (power-on reset) or PROGRAM_B when low.
  • Clears the whole configuration memory
  • Samples the mode pins to determine the configuration mode, master or slave, bit-serial or parallel.
  • Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks for the proper device code and ends with a cyclic redundancy check (CRC) of the complete bitstream.
  • Starts a user-defined seuence of events: realising the internal reset of flip-flops, optionally waiting for the DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to high.

Internal configuration interfaces

The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial flash PROM. The Spartan-6 can also configure itself via a BPI when connected to an industry-standard parallel NOR flash. Note that BPI configuration is not supported in the XC6LX4, XC6SLX25, and XC6LX25T nor is BPI available when using Spartan-6 FPGAs in TQG114 and CPG196 packages. The Spartan-6 LX9 MicroBoard only supports SPI configuration.

External configuration interfaces

The Spartan-6 LX9 MicroBoard has two external interfaces for configuring the FPGA. There is a traditional Platform Cable JTAG header on the bottom of the board (J6) and a new on-board USB-to-JTAG circuit. Both interfaces offer the ability to configure the FPGA and program the on-board serial flash, as well as other Xilinx JTAG functions like ChipScope and SDK Debugger.

Power must be applied to the MicroBoard. This is done by connecting the board via a MicroUSB cable. Plug the cable into the Type-A USB connector, J3, as shown below. Connect the external programming cable to the host PC and to the JTAG port, J6. 

Configuring the Spartan-6 upon power-up

The Spartan-6 FPGA is pre-set to Master Serial Mode, which means it initiates configuration upon power-up and generates a configuration clock. It reads configuration data from an on-board Micron 128Mb Serial Flash memory. This flash can be programmed through either of the two aforementioned interfaces. This tutorial will illustrate how to use these interfaces to configure the FPGA and program the on-board serial flash. For more information see the document: "Configuring the Xilinx Spartan-6 LX9 MicroBoard" found in the Avnet Design Resource Center

More reading

LX9 MicroBoard configuration logic

This blockdiagram shows in simplified form the logic involved when configuring the FPGA.

Configure the FPGA from external source

There are many ways to configure the Spartan-6 FPGA on the MicroBoard from an external source. Let's look at the alternatives.

  • Using Xilinx Platform Studio (XPS)
  • Using Xilinx Software Development Kit (XSDK)
  • Using iMPACT GUI stand-alone
  • Using iMPACT batch mode

In XPS select Device Configuration->Download Bitstream

In Xilinx SDK click the Program FPGA icon.

Using iMPACT in GUI mode and select the configuration file to be used.

Using iMPACT in batch mode. Here is input file:

Run the script.

The FPGA is configured.

Programming the serial (SPI) flash

This board provides several ways to program the serial flash:

  1. iMPACT indirect SPI programmimg via on-board USB to JTAG interface
  2. iMPACT indirect SPI programming via external JTAG cable
  3. SFUTIL direct programming via on-board USB to SPI interface (Windows only)
  4. File transfers using ethernet and TFTP server

In this tutorial we will look at methods 1 and 4.

Programming via the on-board USB to JTAG circuitry

This board incorporates an on-board USB-JTAG access circuit that eliminates the need for an external Xilinx JTAG cable. The on-board JTAG is compatible with all Xilinx tools, including iMPACT, ChipScope, and SDK Debugger. 

The on-board USB programming circuit interfaces to a PC via an Atmel AT90USB162 Full-Speed USB microcontroller. This microcontroller is pre-programmed by Digilent to translate USB-to-JTAG and thus providing access to the on-board JTAG chain. Since this is a Full-Speed USB interface, it will not perform as fast as Hi-Speed USB interfaces. So if faster performance is required for programming or debugging, the Xilinx Platform Cables or a High-Speed Digilent USB cable (JTAG-HS1) can be used.

There are two methods of using this on-board USB-JTAG circuitry. One uses iMPACT software that is included with Xilinx ISE design tools. This method gives you all the access to the FPGA that the Platform Cable solution provides. The other method uses a Digilent programming utility called SFUTIL.exe, which is run via a command line batch file. This utility only programs the attached serial flash and is much faster than using the iMPACT GUI. The only problem for us is there is no Linux version.

Programming the SPI flash through JTAG

We will use iMPACT to transfer the bitstream file to the SPI flash. Here is the setup. To program the SPI flash we need to convert the bitstream file to a Flash PROM image. We can use the program promgen to do that, but the first time we will use iMPACT for the complete flow. Let's start iMPACT.

--> impact &

We will create a new project

and start by preparing a Flash PROM file.

The PROM File Formatter window opens. We will start by selecting storage device type. In step 1 we select the SPI Flash to configure a single FPGA.

In step 2 we add the 128 MB SPI Flash.

In step 3 we enter location, name and, format of the Flash PROM file.

Click OK.

We are ready to add the bitstream file (download.bit).

Double-click <Generate File> to generate the Flash PROM file.

The generate succeded.

Here is the result. 

We have generated the Flash PROM file. Restart iMPACT and select <Configure devices using Boundary-Scan (JTAG)>

The board and the FPGA is connected.

We can identify the FPGA. It is time to add the SPI flash.

Right-click the SPI/BPI item and select ADD SPI/BPI Device and select attached SPI device.

Here is the result.

Select the FLASH and double-click the Program entry to start the programming.

Here is the printout.

Congratulations we are done.

Master SPI Dual and Quad read commands

The Master SPI configuration mode in Spartan-6 FPGAs supports the SPI flash memory dual (x2) and quad bit (x4) memory read commands. To enable this configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode. For more information see document Xilinx UG380 Spartan-6 FPGA Configuration User Guide. Here is a description on how to change from x1 to x4 memory read command. We will run the bitgen command in batch mode. First we have to edit the file bitgen.ut. We will add the following line: -g SPI_buswidth:4

--> cd ..../LX9_LXN/implementation

--> more bitgen.ut

--> bitgen -w -f bitgen.ut LX9_LXN_system

This command generates the file LX9_LXN_system.bit. We can now startup XPS and execute the< Download Bitstream> command which will generate a new download.bit file for us.

We will use this bitstream file to generate a new Flash PROM file following the same setup. Here is the printout from iMPACT when using the new download.bit file. This time the programming is running in x4 mode.

It seems to me the x4 programming mode works much better. This time the automatic board boot-up works just fine. We are ready to add the Linux image to the SPI flash. See the next part of this tutorial.

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