New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, December 13, 2011
FPGA design from scratch. Part 87

Using PlanAhead

The PlanAhead tool is a design and analysis product that provides an intuitive environment for the entire FPGA design and implementation process. To allow a seamless design experience for Xilinx FPGA designers, the PlanAhead tool is integrated with:

  • Xilinx ISE® Design Suite software tools for synthesis and implementation
  • Xilinx® Synthesis Technology (XST) tool
  • CORE GeneratorTM tool
  • ChipScopeTM Pro debugging tool
  • ISE Simulator (ISim) tool
  • XPower Analyzer tool
  • FPGA Editor tool
  • iMPACT device programming tool

According to Xilinx the long term plan is to promote PlanAhead to be the primary design entry GUI and it will eventually replace Project Navigator. Let's find out how good it is. We will jump in the cold water and start PlanAhead.

Starting PlanAhead

--> source /opt/Xilinx/13.3/ISE_DS/
--> planAhead &

Here is the welcome window.

Create a new project

We click the Create New Project Link to start a new project.

We have to give a name and location to our new project.

We will take the synthesized netlists from our last project.

Here are all the netlist files. Don't forget to change the top design (LX9_LXN_system.ngc)

Here are all the constraint files that will be added.

Specify our target FPGA.

Here is a summary of our new project.

PlanAhead up and running.

Adding BMM file

Block Memory Map file. A BMM file is a text file that has syntactic descriptions of how individual block RAMs constitute a contiguous logical data space. Data2MEM uses BMM files to direct the translation of data into the proper initialization form. Since a BMM file is a text file, it is directly editable.

Implement the design

The first attempt to run the implementation failed with the error message "No more space in device".  The first thing we will do is to set the environment variable XIL_PAR_ENABLE_LEGALIZER 


Next we have to modify the settings to improve the mapping of LUTs. Let's open the settings window. 

Running the build program

Here is command to run the ngbuild:

Running the map program

This is what the mapping command looks like after changing the settings. Let's see if this works.

The implementation passed

Here are some of the results displayed in PlanAhead.

Resources used

Primitive statistics

FPGA device

Generate bitstream

Select <Generate Bitstream> from the Program and Debug menu and add the first-stage bootloader ELF file.

Start bitstream generation.

Configure the Spartan-6 FPGA

We will start iMPACT to configure the FPGA. Select iMPACT from the Program and Debug menu.

iMPACT will start automatically and connect to the board and find the FPGA. Select the FPGA and double-click Program.

The device is programmed successfully. If iMPACT quits during startup try to delete the file impactdefaultproj.ipf.


PlanAhead is full of new features which will take some time to master. Xilinx has released a number of training videos helping us to better understand the possibilities.


PlanAhead seems like a good replacement for ISE Project Navigator. There is still a few things to fix and cleanup but I am ready to move from ISE to PlanAhead for the rest of this project.

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