New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


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New Horizons
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

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38000 feet above see level
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Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
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d9 Tech Blog
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EDA DesignLine
Eli's tech Blog
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Friday, February 14, 2014
Zynq design from scratch. Part 10.
Introduction to Zynq. Lab 1

This lab guides us through the process of using Vivado to create a simple ARM Cortex-A9 based processor design targeting the ZedBoard development board. We will use Vivado to create the hardware system and SDK (Software Development Kit) to create an example application to verify the hardware functionality.

When we have completed lab 1, we will know how to do the following:
  • Create a new project in Vivado targeting the Zynq Zedboard
  • Add an embedded ARM source in Vivado integrator
  • Configure the embedded source
  • Enable and map a Zynq PS UART peripheral
  • Build the hardware platform and export to Vivado SDK
  • Create and run a Hello World application

Let's launch Vivado.

vivado &

Start a new project

To start a new project select "Create New Project

Enter the project name LED_Controller and specify the project location. Don't forget to mark the "Create project subdirectory" tick box .

Select project type. In this project we will add RTL source code, synthesize and implement. We will not add any source code at this time.

We will add our design to the ZedBoard.

Click Finish to start project creation. 
The Vivado Cockpit window opens.

Project settings

Before we start designing the new project let's look at the project settings.

Select Tools->Project Settings from the top menu.

We will use Verilog as our target HDL language all other settings can be left with their default values.

Vivado IP Integrator

The current project is blank. To access the ARM processing system, we will create a Block Design in Vivado IP Integrator. Once the Block Design is created, we will add the ARM procesing system as an IP and configure it.

1. Click "Create Block Design" under IP Integrator in the Flow Navigator window.

2. Type system for the Design name and click OK.

3. The source system ( is created and added under Design Sources in the Sources pane to the left and the Diagram opens in the Block Design pane to the right. To get started select <Add IP> by clicking the highlighted text at the top.

4. A pop-up window opens. Type zynq in the search fields and select ZYNQ7 Processing System followed by <ENTER>.

5. ZYN7 Processing System is now added in the Diagram pane. Start to configure the block by double-clicking the IP.

The Re-Customize IP window opens showing the ZYNQ Block Design. Since we specified the board, the ARM processing system is pre-configured with the I/O peripherals that are connected on that board.


7. We will not connect anything from the programmable logic (PL) in our first design and hence we will get an error unless we remove the AXI interface to the PL. Select <PS-PL Configuration> in the Page Navigator pane and expand GP Master AXI Interface. Disable the M AXI GPIO Interface by clicking in the box to remove the check mark.

In Vivado 2015.1 the M AXI GP0 interface can be found here.

8. We will only use UART 1 as a peripheral in our first design and later on we will need SD 0 when we boot from SD card. All other unnecessary connections can be removed. Select <MIO Configuration> in the Page Navigator pane and expand Memory Interfaces, I/O Peripherals and Application Processor Unit. Deselect everything except SD 0  and UART 1. Verify that MIO 40..45 are selected for SD 0 and MIO 48..49 for UART 1.

9. We will not connect anything from the programmable logic in our first design and we don't need to clock the PL. Select <Clock Configuration> in the Page Navigator pane and expand PL Fabric Clocks. Disable FCLK_CLK0.

10. Click OK to close the Re-Customize IP widow. Back in the Diaagram tab we need to create external connections in order to hook up the memory interface and the UART to physical pins. This step can be automated. Start <Run Block Automation> by clicking on the highlighted text at the top of the window and select /processing_system7_0.

11. A pop-up window appears, click OK to run block automation.

12. Verify that the external connections for FIXED_IO (all peripherals connected through MIO) and DDR (the external memory interface) get added. Validate design by clicking on the icon to be found to the left (third from the bottom).

13. A pop-up window appears, verify that there are no errors and click OK.

In Vivado 2015.1 the finished design looks like this.

14. Save the Block Design by typing Ctrl-S or clicking the Save Block Design icon in the top menu bar.

Top   Previous   Next

Posted at 22:23 by

November 14, 2014   10:45 PM PST
When i follow your tutorial,i get the following message when i make the top module
"Top module 'system_wrapper' is currently invalid in Design Sources. What would you like to do?"
Please guide me through it
November 10, 2014   03:32 PM PST
Previously I said that disabling "apply board preset" during "Run Block Automation" prevents the system to be reconfigured in a wrong way, for instance it enables the "M AXI GPIO Interface" over again.

That is true, BUT the fact is that it also configures (if it's enabled) something essential for the correct system settings!

So "apply board preset" during "Run Block Automation" has NOT to be disabled, even if (at least in my case) that does mean to disable "M AXI GPIO Interface" and stuff over again.
September 29, 2014   03:48 AM PDT

"m_AXI_GPO_ACLK, TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN etc problem"

This problem shows up if during "Run Block Automation" the "apply board preset" is checked.
September 23, 2014   03:41 PM PDT
In 2014.02 the project settings dialog is marginally different. However, if I specify "system_wrapper" as top module name as shown I get an error later saying that system_wrapper is invalid.
August 11, 2014   06:49 PM PDT
TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN doesnt appear

And m_AXI_GPO_ACLK and M_AXI_GP0 are removed again after Run Block automation
Is this OK?
August 11, 2014   05:49 PM PDT
Solved, they are extra selected items
Thank you
August 11, 2014   05:49 PM PDT
Solved, they are extra selected items
Thank you
August 11, 2014   05:45 PM PDT
Thank you for this great tutorial :)
I use the same steps for the board zynq 702
the processing system block contains m_AXI_GPO_ACLK and M_AXI_GP0 without TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN
Please help me what to do as an error appears
[BD 41-758] The following clock pins are not connected to a valid clock source:


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