Zynq design from scratch. Part 10. « New Horizons Zynq Blog

Friday, February 14, 2014

Zynq design from scratch. Part 10.

Introduction to Zynq. Lab 1

This lab guides us through the process of using Vivado to create a simple ARM Cortex-A9 based processor design targeting the ZedBoard development board. We will use Vivado to create the hardware system and SDK (Software Development Kit) to create an example application to verify the hardware functionality.

When we have completed lab 1, we will know how to do the following:

Create a new project in Vivado targeting the Zynq Zedboard
Add an embedded ARM source in Vivado integrator
Configure the embedded source
Enable and map a Zynq PS UART peripheral
Build the hardware platform and export to Vivado SDK
Create and run a Hello World application

Let's launch Vivado.

vivado &

Start a new project

To start a new project select "Create New Project".

Enter the project name LED_Controller and specify the project location. Don't forget to mark the "Create project subdirectory" tick box .

Select project type. In this project we will add RTL source code, synthesize and implement. We will not add any source code at this time.

We will add our design to the ZedBoard.

Click Finish to start project creation. The Vivado Cockpit window opens.

Project settings

Before we start designing the new project let's look at the project settings.

Select Tools->Project Settings from the top menu.

We will use Verilog as our target HDL language all other settings can be left with their default values.

Vivado IP Integrator

The current project is blank. To access the ARM processing system, we will create a Block Design in Vivado IP Integrator. Once the Block Design is created, we will add the ARM procesing system as an IP and configure it.

1. Click "Create Block Design" under IP Integrator in the Flow Navigator window.

2. Type system for the Design name and click OK.

3. The source system (system.bd) is created and added under Design Sources in the Sources pane to the left and the Diagram opens in the Block Design pane to the right. To get started select <Add IP> by clicking the highlighted text at the top.

4. A pop-up window opens. Type zynq in the search fields and select ZYNQ7 Processing System followed by <ENTER>.

5. ZYN7 Processing System is now added in the Diagram pane. Start to configure the block by double-clicking the IP.

The Re-Customize IP window opens showing the ZYNQ Block Design. Since we specified the board, the ARM processing system is pre-configured with the I/O peripherals that are connected on that board.

7. We will not connect anything from the programmable logic (PL) in our first design and hence we will get an error unless we remove the AXI interface to the PL. Select <PS-PL Configuration> in the Page Navigator pane and expand GP Master AXI Interface. Disable the M AXI GPIO Interface by clicking in the box to remove the check mark.

In Vivado 2015.1 the M AXI GP0 interface can be found here.

8. We will only use UART 1 as a peripheral in our first design and later on we will need SD 0 when we boot from SD card. All other unnecessary connections can be removed. Select <MIO Configuration> in the Page Navigator pane and expand Memory Interfaces, I/O Peripherals and Application Processor Unit. Deselect everything except SD 0 and UART 1. Verify that MIO 40..45 are selected for SD 0 and MIO 48..49 for UART 1.

9. We will not connect anything from the programmable logic in our first design and we don't need to clock the PL. Select <Clock Configuration> in the Page Navigator pane and expand PL Fabric Clocks. Disable FCLK_CLK0.

10. Click OK to close the Re-Customize IP widow. Back in the Diaagram tab we need to create external connections in order to hook up the memory interface and the UART to physical pins. This step can be automated. Start <Run Block Automation> by clicking on the highlighted text at the top of the window and select /processing_system7_0.

11. A pop-up window appears, click OK to run block automation.

12. Verify that the external connections for FIXED_IO (all peripherals connected through MIO) and DDR (the external memory interface) get added. Validate design by clicking on the icon to be found to the left (third from the bottom).

13. A pop-up window appears, verify that there are no errors and click OK.

In Vivado 2015.1 the finished design looks like this.

14. Save the Block Design by typing Ctrl-S or clicking the Save Block Design icon in the top menu bar.

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Posted at 22:23 by


	Saher November 14, 2014 10:45 PM PST Hello, When i follow your tutorial,i get the following message when i make the top module "Top module 'system_wrapper' is currently invalid in Design Sources. What would you like to do?" Please guide me through it


	Sergio_Avramenko November 10, 2014 03:32 PM PST Previously I said that disabling "apply board preset" during "Run Block Automation" prevents the system to be reconfigured in a wrong way, for instance it enables the "M AXI GPIO Interface" over again. That is true, BUT the fact is that it also configures (if it's enabled) something essential for the correct system settings! So "apply board preset" during "Run Block Automation" has NOT to be disabled, even if (at least in my case) that does mean to disable "M AXI GPIO Interface" and stuff over again.


	Sergio_Avramenko September 29, 2014 03:48 AM PDT Hi, "m_AXI_GPO_ACLK, TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN etc problem" This problem shows up if during "Run Block Automation" the "apply board preset" is checked.


	Petter September 23, 2014 03:41 PM PDT In 2014.02 the project settings dialog is marginally different. However, if I specify "system_wrapper" as top module name as shown I get an error later saying that system_wrapper is invalid.


	Hanaa August 11, 2014 06:49 PM PDT TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN doesnt appear And m_AXI_GPO_ACLK and M_AXI_GP0 are removed again after Run Block automation Is this OK?


	Hanaa August 11, 2014 05:49 PM PDT Solved, they are extra selected items Thank you


	Hanaa August 11, 2014 05:49 PM PDT Solved, they are extra selected items Thank you


	Hanaa August 11, 2014 05:45 PM PDT Thank you for this great tutorial :) I use the same steps for the board zynq 702 the processing system block contains m_AXI_GPO_ACLK and M_AXI_GP0 without TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN Please help me what to do as an error appears [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK

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