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Friday, February 14, 2014 |
Zynq design from scratch. Part 10.
Posted at 22:23 by
 |  |  | Saher November 14, 2014 10:45 PM PST
Hello,
When i follow your tutorial,i get the following message when i make the top module
"Top module 'system_wrapper' is currently invalid in Design Sources. What would you like to do?"
Please guide me through it |  |
  |  |  | Sergio_Avramenko November 10, 2014 03:32 PM PST
Previously I said that disabling "apply board preset" during "Run Block Automation" prevents the system to be reconfigured in a wrong way, for instance it enables the "M AXI GPIO Interface" over again.
That is true, BUT the fact is that it also configures (if it's enabled) something essential for the correct system settings!
So "apply board preset" during "Run Block Automation" has NOT to be disabled, even if (at least in my case) that does mean to disable "M AXI GPIO Interface" and stuff over again. |  |
  |  |  | Sergio_Avramenko September 29, 2014 03:48 AM PDT
Hi,
"m_AXI_GPO_ACLK, TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN etc problem"
This problem shows up if during "Run Block Automation" the "apply board preset" is checked.
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  |  |  | Petter September 23, 2014 03:41 PM PDT
In 2014.02 the project settings dialog is marginally different. However, if I specify "system_wrapper" as top module name as shown I get an error later saying that system_wrapper is invalid. |  |
  |  |  | Hanaa August 11, 2014 06:49 PM PDT
TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN doesnt appear
And m_AXI_GPO_ACLK and M_AXI_GP0 are removed again after Run Block automation
Is this OK? |  |
  |  |  | Hanaa August 11, 2014 05:49 PM PDT
Solved, they are extra selected items
Thank you |  |
  |  |  | Hanaa August 11, 2014 05:49 PM PDT
Solved, they are extra selected items
Thank you |  |
  |  |  | Hanaa August 11, 2014 05:45 PM PDT
Thank you for this great tutorial :)
I use the same steps for the board zynq 702
the processing system block contains m_AXI_GPO_ACLK and M_AXI_GP0 without TTC0_CLK0_IN, TTC0_CLK1_IN ,TTC0_CLK2_IN
Please help me what to do as an error appears
[BD 41-758] The following clock pins are not connected to a valid clock source:
/processing_system7_0/M_AXI_GP0_ACLK
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