New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


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and ask questions or make comments
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New Horizons
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

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The New York City Marathon

Kittelfjall Lappland

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38000 feet above see level
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Landsort Art Walk
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100 Power Tips for FPGA Designers

Adventures in ASIC
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d9 Tech Blog
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EDA DesignLine
Eli's tech Blog
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Monday, February 24, 2014
Zynq design from scratch. Part 16.
Adding a GPIO peripheral

Are you ready for lab 2? This lab will show how to add a custom PL peripheral to the embedded system. When we have completed lab 2, we will know how to do the following:
  • Add a GPIO interface to the Processing Subsystem (PS).
  • Export signals, including clocks from the PS to the Programmable Logic subsection (PL)
  • Modify the top level HDL module
  • Create and connect a new custom HDL module
  • Connect package pins
  • Implement the design and export the bitfile to SDK
  • Create a new software project
  • Access addresses and parameters defined in the Xparameters.h file
  • Write a simple C application
  • Download and test the software application in hardware
  • Use the SDK debugger to step through our software application

Work flow

This pictures shows the work flow we will follow in this lab.

We will continue from lab 1 and open our old project in Vivado. Let's start Vivado.

vivado &

1. Click "Open Project" and open the lab1 project.

2. Expand system_wrapper in the Source panel and double-click system_i - system ( to open Block Diagram.

3. The processing system opens in the Block Diagram window.

4. Select Add IP by clicking the +icon to the left. A pop-up search window opens.Type gpio in the search field and select AXI GPIO followed by <Enter>.

5. AXI_GPIO is now added in the Diagram pane. Start to configure the block by double-clicking the IP.

6. The Re-Customize Ip window opens showing the AXI GPIO. Select the IP Configuration tab and check the settings for All Outputs. Note the GPIO width is set to 32 bits. That is OK as we will be writing 32-bit values out to the GPIO. Click OK.

7. The AXI GPIO IP will be implemented in the PL, but before we can connect it to the AXI interconnect we need to enable the Master AXI interface on the PS. Start to configure the PS block by double-clicking ZYNQ7 PS.

8. The Re-Customize IP window opens showing the ZYNQ Block Design. Select PS-PL Configuration in the Page Navigator pane to the left and expand GP MAster AXI Interface. Enable the M AXI GPIO Interface ticking the box.

9. We will also need a clock to the PL that can be used by the logic connected to the GPIO interface. Select Clock Configuration in the Page Navigator pane and expand PL Fabric Clocks. Enable FCLK_CLK0 by ticking the box and change the Requested Frequency to 50 MHz as well.

10. Click OK to close the Re-Customize IP window. Back in the Diagram pane we need to create the AXI interconnect. This step can be automated. Start Run Connection Automation by clicking on the highlighted text at the top of the window and select /axi_gpio_1/s_axi.

11. A pop-up window appears, click OK to Run Connection Automation.

12. Improve the appearance by clicking the Regenerate Layout icon to the left.

13. We also need to create external connections from the block design that we can hook up to the rest of the logic in PL. Right-click on the gpio pin interface symbol on the AXI GPIO block and select Make External.

14. Select the GPIO port and rename the external interface from gpio to LED_DutyCycle in the External Interface Propertied pane.

15. The final connection that needs to be made in the block design is to create an external port for the clock to the PL. Right-click on the FCLK_CLK0 pin symbol on the ZYNQ block and select Create Port.

16. Verify that the right pin was selected and click OK.

17. Improve the appearance by clicking Regenerate Layout and verify the connectivity by clicking Validate Design.

18. Here is the final design.

19. Save the block design by typing Ctrl-S or clicking the Save Block Design icon in the top menu.

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