Adding a GPIO peripheral
Are you ready for lab 2? This lab will show how to add a custom PL peripheral to the embedded system. When we have completed lab 2, we will know how to do the following:
- Add a GPIO interface to the Processing Subsystem (PS).
- Export signals, including clocks from the PS to the Programmable Logic subsection (PL)
- Modify the top level HDL module
- Create and connect a new custom HDL module
- Connect package pins
- Implement the design and export the bitfile to SDK
- Create a new software project
- Access addresses and parameters defined in the Xparameters.h file
- Write a simple C application
- Download and test the software application in hardware
- Use the SDK debugger to step through our software application
This pictures shows the work flow we will follow in this lab.
We will continue from lab 1 and open our old project in Vivado. Let's start Vivado.
1. Click "Open Project" and open the lab1 project.
2. Expand system_wrapper in the Source panel and double-click system_i - system (system.bd) to open Block Diagram.
3. The processing system opens in the Block Diagram window.
4. Select Add IP by clicking the +icon to the left. A pop-up search window opens.Type gpio in the search field and select AXI GPIO followed by <Enter>.
5. AXI_GPIO is now added in the Diagram pane. Start to configure the block by double-clicking the IP.
6. The Re-Customize Ip window opens showing the AXI GPIO. Select the IP Configuration tab and check the settings for All Outputs. Note the GPIO width is set to 32 bits. That is OK as we will be writing 32-bit values out to the GPIO. Click OK.
7. The AXI GPIO IP will be implemented in the PL, but before we can connect it to the AXI interconnect we need to enable the Master AXI interface on the PS. Start to configure the PS block by double-clicking ZYNQ7 PS.
8. The Re-Customize IP window opens showing the ZYNQ Block Design. Select PS-PL Configuration in the Page Navigator pane to the left and expand GP MAster AXI Interface. Enable the M AXI GPIO Interface ticking the box.
9. We will also need a clock to the PL that can be used by the logic connected to the GPIO interface. Select Clock Configuration in the Page Navigator pane and expand PL Fabric Clocks. Enable FCLK_CLK0 by ticking the box and change the Requested Frequency to 50 MHz as well.
10. Click OK to close the Re-Customize IP window. Back in the Diagram pane we need to create the AXI interconnect. This step can be automated. Start Run Connection Automation by clicking on the highlighted text at the top of the window and select /axi_gpio_1/s_axi.
11. A pop-up window appears, click OK to Run Connection Automation.
12. Improve the appearance by clicking the Regenerate Layout icon to the left.
13. We also need to create external connections from the block design that we can hook up to the rest of the logic in PL. Right-click on the gpio pin interface symbol on the AXI GPIO block and select Make External.
14. Select the GPIO port and rename the external interface from gpio to LED_DutyCycle in the External Interface Propertied pane.
15. The final connection that needs to be made in the block design is to create an external port for the clock to the PL. Right-click on the FCLK_CLK0 pin symbol on the ZYNQ block and select Create Port.
16. Verify that the right pin was selected and click OK.
17. Improve the appearance by clicking Regenerate Layout and verify the connectivity by clicking Validate Design.
18. Here is the final design.
19. Save the block design by typing Ctrl-S or clicking the Save Block Design icon in the top menu.
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