New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

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38000 feet above see level
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Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

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d9 Tech Blog
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EDA DesignLine
Eli's tech Blog
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FPGA Journal
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Lesley Shannon Courses
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Programmable Logic DesignLine
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Wednesday, February 26, 2014
Zynq design from scratch. Part 17.
Create a new custom HDL module

Since we have added the AXI GPIO in the design we need to regenerate the HDL files that are required for synthesis, implementation, and simulation. Expand Design Sources and system_wrapper in the Source pane, right-click system ( and select Generate Output Files. Click Generate to start generating the output products.

Create HDL wrapper file

We also need to generate a new system_wrapper file.
Right-click system ( and select: Create HDL Wrapper.

We will copy and overwrite the old file.

Here is the new wrapper file showing the system instance. Leave the file open we will use it soon.

Create a pulse-width modulation module

Next we need to create a new HDL module that will control the LED brightness. We will use pulse-width modulation (PWM) technique. This module will need a free running counter and a comparator that determines the duty cycle of the output signal. Most LCD monitors refresh rate is 50-60 Hz. From the PS we output a 50 MHz clock. Dividing that clock by one million will give a 50 Hz refresh rate. The corresponding duty cycle will then control the brightness. If we don't have time to write this code ourselves we can download a Verilog HDL file called PWM_Controller.v

Add sources

After downloading PWM_Controller.v w ehave to add it to our design. In the Flow Navigator pane select Project Manager->Add Sources.

Select Add or Create Design Sources and click Next.

Find and select the PWM_Controller.v file and click OK.

Mark Copyt sources into project and click Finish.

The Verilog HDL file PWM_Controller.v has been added to the Design Sources.

Modifying the wrapper file

We will make the following changes to the system_wrapper.v file:

Remove unused outputs FCLK_CLK0 and led_dutycycle_tri_0. We don't have bring out these signals to output pins. We will remove them from the module header and the output declaration. We will also add the LEDS port.

2. Add a LED 8 bit output in the module header and in the output declaration.

3. Add an instantiation of the PWM_Controller.v and connect all the signals.

Here is the modified system_wrapper.v file. Save the file by clicking CTRL-S

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Posted at 15:50 by

December 24, 2014   08:23 PM PST
Well, thank You it helped me a lot :)
November 25, 2014   07:40 PM PST
Could You please show how to the wrapper file in VHDL instead of Verilog?
September 21, 2014   04:00 AM PDT
At the beginning there should be a correction, I think we should <Create Wrapper>, instead of <Select Output Files>

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