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Since we have added the AXI GPIO in the design we need to regenerate the HDL files that are required for synthesis, implementation, and simulation. Expand Design Sources and system_wrapper in the Source pane, right-click system (system.bd) and select Generate Output Files. Click Generate to start generating the output products.
Create HDL wrapper file
We also need to generate a new system_wrapper file. Right-click system (system.bd) and select: Create HDL Wrapper.
We will copy and overwrite the old file.
Here is the new wrapper file showing the system instance. Leave the file open we will use it soon.
Create a pulse-width modulation module
Next we need to create a new HDL module that will control the LED brightness. We will use pulse-width modulation (PWM) technique. This module will need a free running counter and a comparator that determines the duty cycle of the output signal. Most LCD monitors refresh rate is 50-60 Hz. From the PS we output a 50 MHz clock. Dividing that clock by one million will give a 50 Hz refresh rate. The corresponding duty cycle will then control the brightness. If we don't have time to write this code ourselves we can download a Verilog HDL file called PWM_Controller.v
Add sources
After downloading PWM_Controller.v w ehave to add it to our design. In the Flow Navigator pane select Project Manager->Add Sources.
Select Add or Create Design Sources and click Next.
Find and select the PWM_Controller.v file and click OK.
Mark Copyt sources into project and click Finish.
The Verilog HDL file PWM_Controller.v has been added to the Design Sources.
Modifying the wrapper file
We will make the following changes to the system_wrapper.v file:
1. Remove unused outputs FCLK_CLK0 and led_dutycycle_tri_0. We don't have bring out these signals to output pins. We will remove them from the module header and the output declaration. We will also add the LEDS port.
2. Add a LED 8 bit output in the module header and in the output declaration.
3. Add an instantiation of the PWM_Controller.v and connect all the signals.
Here is the modified system_wrapper.v file. Save the file by clicking CTRL-S
Michal December 24, 2014 08:23 PM PST Well, thank You it helped me a lot :)
Michal November 25, 2014 07:40 PM PST Could You please show how to the wrapper file in VHDL instead of Verilog?
L30nardoSV September 21, 2014 04:00 AM PDT At the beginning there should be a correction, I think we should <Create Wrapper>, instead of <Select Output Files>
