New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


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New Horizons
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

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Kittelfjall Lappland

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38000 feet above see level
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100 Power Tips for FPGA Designers

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Eli's tech Blog
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Friday, February 28, 2014
Zynq design from scratch. Part 18.
Connect package pins and implement design

We need to clarify which external package pins that should be used to connect the LEDS output from the PWM_controller in the PL to the physical LEDs on the PCB. In order to pick up all the signal names, the design needs to be synthesized before the I/O planning layout can be opened.


Synthesis is the process of transforming an RTL-specified design into a gate-level representation. Vivado Integrated Design Environment (IDE) synthesis is timing-driven and optimized for memory usage and performance. Support for SystemVerilog as well as mixed VHDL and Verilog languages is included. The tool supports Xilinx Design Constraints (XDC), which is based on the industry-standard Synopsys Design Constraints (SDC). For more information read the document: Vivado Design Suite User Guide Synthesis (UG901).

1. In the Flow Navigator pane, select Synthesis->Run Synthesis. This will take a few minutes to complete. Ignore and close any warnings.


If the synthesis runs without errors this window will pop up.

2. Select Open Synthesis Design and click OK. Here is the result after synthesis.

Pin placement

3. To start the pin placement change from Default Layout to I/O planning layout in the top toolbar.

4. Expand All Ports in the I/O Planning pane at the bottom. Scroll down and select bus LEDS.

5. To find out which pins are connected to the LEDs we can read the ZedBoard Hardware Guide. We find the information in chapter 2.7.2 User LEDs.

6. Change the I/O standard to LVCMOS33 (3.3V) and add the pin locations in the Site column.

7. Save the settings in a constraints file by clicking CTRL-S.

8. A pop-up window appears. Type the file name PL_pins and click OK.

9. Returning to Default Layout we can see the file in the Design Sources pane. This is what the file PL_pins.xdc looks like.

Here is what the Linux file structure looks like for the LED_Controller project.


The Vivado Design Suite offers a variety of design flows, and supports an array of design sources. However, to get to a bitstream that can be downloaded into an FPGA, the design must pass through implementation. This is a series of steps that takes the logical netlist and maps it into the physical array of the target Xilinx device.

The Vivado implementation process includes logical as well as physical transformations of the design, and consists of the following sub-processes:

  1. Opt Design: Optimize the logical design to make it easier to fit into the target Xilinx FPGA.
  2. Power Opt Design: Optionally optimize elements of the design to reduce power demands of the implemented FPGA.
  3. Place Design: Place the design onto the target Xilinx device.
  4. Phys Opt Design: Optionally optimize the timing of the design by replicating drivers of high-fanout nets to distribute the loads.
  5. Route Design: Route the design onto the target Xilinx device.
  6. Write Bitstream: Generate a bitstream for Xilinx device configuration. 

For more information read the document: Vivado Design Suite User Guide Implementation (UG904).

Out of date design

Saving the constraint file caused the synthesis to go out-of-date.

1. To avoid re-running the synthesis we can force the design up-to-date by selecting the run in Design Runs tab, right click and select "Force Up-to-Date".

2. In the Flow Navigator pane, select Run Implementation. This will take a few minutes to complete.

3. If the implementation returns without errors this window pops up.

4. Let's open the implemented design and have a look at the result.

5. From the Flow Navigator we can look a number of reports.

6. Here is the utilization report. We can see that we use only a small fraction of the resources available.

Bitstream generation

7. In the Flow Navigator pane, select Generate Bitstream. This will take a few minutes to complete.

8. When the bitstream generation has finished this window pops up.

9. Click OK to view the result.

Export hardware for SDK

We now have a design that can be used to configure the ZedBoard. But first we have to export the design to Vivado SDK where we will write the c-program that will run in the ARM processing system. Before we start the export we have to make sure that:
  • The block diagram is displayed in Vivado. Expand system_wrapper in the Source panel and double-click system_i - system ( to open the Block Diagram.
  • SDK is not running
  • The implemented design is open (when exporting the bitstream)

10. To open the implemented design, click Open Implemented Design in the Flow Navigator.

11. In the Vivado top menu select: File->Export->Export Hardware for SDK

12. This time we will export the hardware design and include the bitstream. Click OK.


13. Click Yes to overwrite the old design. This completes the hardware design in lab 2. In the next session we will create a custom C application to interact with this new PL peripheral. Here is what was exported.

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Posted at 09:08 by

December 3, 2015   10:20 AM PST

Thank you for this wonderful help.
I tried to follow the tutorial using the vivado 2015.2 but unable to generate bitstream, there is unconstrained logical ports on FCLK_CLK0.

In I/O Ports tab, there is this CLK_FCLK_CLK0_M_AXI_GPIO... added under ALL ports, before I didn't saw this.

Do you know how to resolve this issue?

July 19, 2014   04:46 PM PDT
Hi Pedro,
Thanks for helping out. I'm having vacation and have no access to the ZedBoard.
July 16, 2014   01:18 PM PDT
Hello Nadine and Huse

You cant choose B14 because B14 is only for PS. You cannot connect B14 to PL in Microzed.
If you want you can connect an LED on the bottom of your board, just check the available pins on the PL part and then select it.
You might want to take a look at the board schematic and see witch pin suits you best.

If you have any other questions you can email me at:
July 12, 2014   03:36 PM PDT
I'm getting the same kind of error for Microzed board:

llegal to place instance LED_OBUF_inst on site B14. The location site type does not match the instance type. Instance LED_OBUF_inst belongs to a shape with reference instance LED_OBUF_inst. Shape elements have relative placement respect to each other.The invalid location might results from a constraint on any of the instance in the shape.

Is it possible to prevent Vivado from placing fixed port in B14 location ?

June 25, 2014   06:11 PM PDT
Do you think it is possible to adapt this to the microzed board? i have modified the code so there is only one led, and then tried to place it in B14 (where the microzed's LED is at. But i get the next error: " Illegal to place instance LEDS_OBUF[0]_inst on site B14. The location site type does not match the instance type. Instance LEDS_OBUF[0]_inst belongs to a shape with reference instance LEDS_OBUF[0]_inst. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape."
Do you have any idea why this could be?

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