New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, July 07, 2009
Zoo Design Platform
It all started back in 1992. My design group at Ericsson was designing a multiprocessor board using Motorola 88000 microprocessors. We needed some fast glue-logic and decided to use Motorola H4C ASICs (0.7um CMOS) to design this logic. I was responsible for the testlogic design, including the tap controller and the boundary scan implementation and was going to use the Verilog hardware description language (HDL) for the first time. I had been to a Verilog training course and I had learned how to use Verilog-XL. Most of time I was debugging my design blocks using Verilog-XL in interactive mode. All the commands had to be written and executed from the command line. Moving up and down the design hierarchy involved many $scopes and $showscopes commands. To save time and typing I decided to create a graphical user interface (GUI) and put all these commands behind buttons and menus.

At that time all our computer work was done on SUN
SPARC machines with the  SUN OS 4 operating system. SUN Microsystems was using OPEN LOOK user interface with the XView toolkit and had a graphical interface builder called Devguide. I started to use this tool and could easily design very nice graphical interfaces. At the same time I learned how to program in "C" and then everything fell into place. My first tool was called VeriSmart.

VeriSmart Simulation Workbench

MultiSmart Cosimulation Workbench

One year later we needed support for co-simulation, running up to six simulations at the same time. The communication between the simulations was done using file semaphores. To support this simulation setup I developed MultiSmart.

Cobra Command Center

Back in those old days the only terminal emulator window you had access to was
cmdtool or shelltool. I guess xterm was around but I hadn't  heard about it. cmdtool and shelltool did not offer anything more than a window to type commands in. The only difference between the two was that cmdtool had a scrolling window. I decided to build my own terminal emulator, Cobra Command Center. I started with a plain cmdtool window and began adding new features.

1. A file tree browser.

2. A menu to support a number of file operations in the file tree.

3. A file list browser.

When there are too many files in a directory a file list browser makes more sense. It also has a filter function that lets you filter out only the files you are interesting in.

4. A command list manager.

The command list manager lets you store all your "always forgot" commands. To execute a command double-click it.


The Bookmark Definition window lets you bookmark any directory, source file, executable file, script file, FrameMaker file and PDF file. When selecting a bookmarked file the appropriate action will be taken. For a directory a cd <bookmark> will be executed.

This is what came out of the remodeling process.

Still today I am using Cobra Command Center for 95% of all the terminal work I do, but now the Linux version.

Mongoose Simulation Environment

During my 15 years as an ASIC designer I was involved in more than 25 ASIC design projects. Every time I had to start from scratch to build a new simulation environment. That struggle gave me the idea to start working on the
Mongoose Simulation Environment.

Why using the Mongoose Simulation Environment:
  • Save time. Faster setup time. Easier to find files.
  • A common interface to all simulators (ModelSim, NCSIM, VCS)
  • Full support for both interactive and batch simulations
  • Seamless integration of Specman
  • Clearcase support for revision control
  • LSF batch queue handling
Read more about using Mongoose in the FPGA design from scratch story.

Zebra Verilog Design Explorer

When designing an ASIC using Verilog HDL you will end up with a huge number of Verilog source files stored in many different directories. When debugging the design you need fast access to all these files to make changes and rerun your simulations.
Zebra Verilog Design Explorer will make that process a very fast and efficient one. Just open the Design Tree Browser and display the part of the design tree you are interested in. Than simply mark the module you would like to change and load it to the text editor window.

The Zebra Design Tree Browser.

Topi - Top Code Generator

Ever heard of table driven design. That is exactly what
Topi is all about. When designing an ASIC with more than 1000 signal pins you need an exact and precise way of adding all the signal names. Topi will help you generate the top testbench, the top instantiation and the ASIC pinlayout in the same tool.

Topi Pin Table Editor

Topi Pin Layout Editor

Porting Unix programs to Linux

Today it is hard to find a SUN SPARC workstation and most of the engineering work is done on Linux based computers or PC. Some years ago I decided to move my Zoo Design Platform to the Linux platform. This was a fairly simple process because all the xview libraries had been converted to Linux.

Porting a Unix program to Mac OS X

As a last step I ported one of the programs to Mac OS X. When Apple moved to Intel based computers it made things much easier. You can read more about this process

Download programs

All the programs can be download from


By now I think you understand why it is called
Zoo Design Platform. Here again are all the "animals" in the Zoo.

 Tool  Description  Introduced  Mac OS X
VeriSmart Verilog Simulation Workbench
1992 No
MultiSmart Verilog Cosimulation Workbench
1993 No
Cobra Command Center (Smart Terminal)
1995 Yes Yes
Mongoose Simulation Environment
1993 No
Zebra Verilog Design Explorer
1994 No
VHDL Design Explorer
Top Code Builder

Welcome to the Zoo!


Posted at 13:18 by

download silabus k13 sd
November 29, 2014   02:16 AM PST
very useful software thank's.. :D
June 19, 2009   07:19 AM PDT
nice tool ....

tool download link please send me

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