New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Saturday, May 03, 2014
Zynq design from scratch. Part 43.
Hardware debugging

When you read this blog it may look like everything just works, but that is not always the case. I have spent many hours trying to understand what is going on inside my ZedBoard. For software debugging we have full access to almost all internal registers and can read and write to memory and set breakpoints and single step our programs. When it comes to hardware debugging we are much more restricted. Let's start by studying the document: "Vivado Design Suite User Guide, Programming and debugging"


Debugging an FPGA design is a multistep, iterative process. Like most complex problems, it is best to break the FPGA design debugging process down into smaller parts by focusing on getting smaller sections of the design working one at a time rather than trying to get the whole design to work at once. Iterating through the design flow by adding one module at a time and getting it to function properly in the context of the whole design is one example of a proven design and debug methodology. We can use this design and debug methodology in any combination of the following design flow stages

  • RTL-level design simulation
  • Post-implemented design simulation
  • In-system debugging
  • Using external instruments

RTL design simulation

The design can be functionally debugged during the simulation verification process. Xilinx provides a full design simulation feature in the Vivado® IDE. The Vivado design simulator can be used to perform RTL simulation of our design. The benefits of debugging our design in an RTL simulation environment include full visibility of the entire design and ability to quickly iterate through the design/debug cycle. The limitations of debugging our design using RTL simulation includes the difficulty of simulating larger designs in a reasonable amount of time in addition to the difficulty of accurately simulating the actual system environment. For more information about using the Vivado simulator, refer to the Vivado Design Suite User Guide: Logic Simulation (UG937)

Post-implemented design simulation

The Vivado simulator can also be used to simulate the post-implemented design. One of the benefits of debugging the post-implemented design using the Vivado simulator includes having access to a timing-accurate model for the design. The limitations of performing post-implemented design simulation include those mentioned in the previous section: long run-times and system model accuracy.

In-system logic design debugging

The Vivado IDE also includes a logic analysis feature that enables us to perform in-system debugging of the post-implemented design an FPGA device. The benefits for debugging our design in-system include debugging our timing-accurate, post-implemented design in the actual system environment at system speeds. The limitations of in-system debugging includes somewhat lower visibility of debug signals compared to using simulation models and potentially longer design/implementation/debug iterations, depending on the size and complexity of the design.

ChipScope Pro and the Serial I/O toolkit

ChipScope™ Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into our design, allowing us to view any internal signal or node, including embedded hard or soft processors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for your design. Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool.

The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and interactive setup and debug of serial I/O channels in high-speed FPGA designs. The ChipScope Pro Serial I/O Toolkit allows us to take bit-error ratio (BER) measurements on multiple channels and adjust high-speed serial transceiver parameters in real-time while your serial I/O channels interact with the rest of the system. To use ChipScope Pro we need a seperate license not included in Vivado WebPACK.

Debugging using external instruments

The possibility to analyze what is going on inside our Zynq device is valuable, but when we want to measure what is happening on our ZedBoard, we have to rely on external instrumentation. Professional logic analyzers and oscilloscopes are expensive instruments (>$1000) and maybe not reachable for our hobby projects. Let's look for a cheaper solution. When looking around I found LogiScope from Oscium.

LogiScope logic analyzer

LogiScope transforms an iPhone, iPad or iPod into a 100MHz, 16 channel logic analyzer. Not only is it the most intuitive logic analyzer available, the triggering is so powerful we'll be able to count the hair on our bugs (not my words). Specifications:

  • 100 MHz, 16 channel logic analyzer
  • Two logic harnesses (each with 8 digital, 1 ground)
  • Protocol decoding: I2C, SPI, UART, Parallel
  • Record length : 1000
  • Maximum input bandwidth : 30MHz
  • Works with 2.0v, 2.5v, 3.3v & 5.0v systems
  • Portable: goes where you go
  • Input voltage -0.5v to +7v
  • Advanced triggering
  • Compatible with Lightning and 30 pin connectors (with adapter, works with iPhone 5 & iPad Mini
  • Price : $200 (€150)

Looks like a perfect instrument for our project. Let's order one. If you live in Europe you can order it from Lab eSHOP. In the rest of the world it can be ordered from the Oscium webpage.


It took a few days and then this box appered on my desk.

Unpacking and connecting

Unpacking and connecting to the ZedBoard took only a few minutes. I have the first generation iPad which I used in my setup.

A closer look at the connection to the ZedBoard. As you can see I am using the Pmod connectors JA1 and JB1. The black wires are connected to ground.

Download and install

The iPad or iPhone app running the Logic Analyzer can be downloaded for free from the Apple AppStore (search for LogiScope).

Adding probes to the design

We have to modify our design to bring out the signals we would like to look at to the Pmod connectors. Here is a description on how to do that. 

1.Find out which Zynq pins are connected to the Pmod connectors. The information can be found in the ZedBoard Hardware Guide.

2. Start Vivado and open the LED_Controller project.

3. Open the system_wrapper.v file and add the PROBE output. We will connect the LEDS PWM signals and the FCLK_CLK0. The unused outputs will be forced to both 0 and 1.


   output [15:0] PROBES;

// Probes used for logic analyzer
   assign PROBES = {7'b1010101,FCLK_CLK0,LEDS};

4. Save the system_wrapper.v file (ctrl-S).

5. Follow the instructions in part 18 to synthesize the design and add new pin locations.

6. Connect the PROBE outputs to the Pmod connectors.

7. Run implementation and generate the new bitstream file.

8. Export design to SDK. Make sure the new bitstream file is exported.

9. Start SDK and connect to the new hardware design.

10. Follow the instructions in part 19 to load the new hardware design and to run the LED_Dimmer program.

11. Turn on the iPad and start the LogiScope app. Select different settings from the terminal and watch the pulse width changing.

To get started

Learn how to get started from this blog at EEweb.

Triggering demos

Oscium has put up three videos on their webpage illustrating the power of the advanced triggering system.


The LogiScope logic analyzer is very easy to setup and to use. It has its limitation when it comes to analyzing high-speed clocks > 30MHz but we can always add some prescaler logic in the programmable logic part before bringing out the signals. I think this instrument can be very useful in our Zynq design project.

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