New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, December 05, 2006
FPGA design from scratch. Part 13
The MicroBlaze soft processor

We will use the
MicroBlaze soft processor as the main controller in our system. The MicroBlaze™ soft processor is a 32-bit Harvard RISC architecture optimized for Xilinx FPGAs. The basic architecture consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt. We can configure this basic design with more advanced features to allow us to balance the required performance of the target application against the logic area cost of the soft processor.

(Courtesy of Xilinx)
Here is the reference guide to

Installation of the Embedded Development Kit (EDK)

The Embedded Development Kit provides you with a complete tool chain for the creation of your Virtex™ and Spartan™ series embedded PowerPC™ 405 and MicroBlaze™ designs. You find all the documentation here.

To install the Linux version of EDK follow these steps.
  1. Download the EDK Get Started  document
  2. Insert the Embedded Development Kit DVD. This DVD is part of the ML401 development kit.
  3. Open a terminal window and type cd /media/cdrom0 or whatever the path is to the cdrom.
  4. Execute the setup script ./setup. If everything goes fine the Xilinx Install Program window will be displayed.
  5. If you get the following error message when running the setup script it probably means that the system doesn't allow you to execute programs on the DVD:  bash: ./setup: /bin/sh: bad interpreter: Permission denied.
  6. To fix this problem you have to edit the file /etc/fstab (static file system information) and add execute permission to the line defining the cdrom. Here is an example:  /dev/hdb  /media/cdrom0   udf,iso9660 user,noauto,exec  0   0
  7. Restart the system and start from 3 again.

  1. Register the EDK software here.
  2. Fill in all information and have the EDK product ID available, found on the back of EDK Development Kit DVD.
  3. The registration code will appear in the web browser and will also be sent to the email address you specified.
  4. Read all license agreements carefully !!! and click the agree check boxes.
  5. Insert the registration code when asked for.
  6. Specify the destination directory where the EDK software will be installed.
  7. Start the installation

When the installation has finished we will see the following file tree structure.

The files settings.csh and contains setting of environment variables used by EDK. If you use a bash or sh shell add the line: source edk_install_dir/ to your shell startup file. If you use csh or tcsh add the line: source edk_install_dir/settings.csh to your shell startup file.

Now it is time to find the MicroBlaze VHDL source code. I wonder where it can be and in what format it is. Let's look in the hw directory.

Protected code

All the IP vendors protect their
intellectual property using different forms of encryption. The MicroBlaze VHDL source code is encrypted and can not be read, modified or understood. It can be compiled using the Cadence ncvhdl compiler and you don't need to specify any special flags for the compilation.

Xilinx libraries

UNISIM library

The UNISIM Library is a library of functional models used for behavioral and structural simulation. It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated, such as I/Os and memory cells. We can instantiate the UNISIM library components in our design (VHDL or Verilog) and  simulate them during behavioral simulation. All asynchronous components in the UNISIM library have zero delay. All synchronous components have a unit delay to avoid race conditions. The clock-to-out delay for these is 100 ps.

SIMPRIM library

The SIMPRIM Library is used for timing simulation. It includes all the Xilinx Primitives Library components used by Xilinx implementation tools.

XilinxCoreLib library

The Xilinx CORE Generator™ is a graphical Intellectual Property (IP) design tool for creating high-level modules like FIR Filters, FIFOs, CAMs, and other advanced IP. We can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices, such as block multipliers, SRLs, fast carry logic and onchip, single-port or dual-port RAM.
The CORE Generator HDL library models are used for behavioral simulation. We can select the appropriate HDL model to integrate into our HDL design. The models do not use library components for global signals.

EDK library

The EDK Library is used for behavioral simulation. It contains all the EDK IP components, precompiled for ModelSim SE and PE or NcSim. This library eliminates the need to recompile EDK components on a per-project basis, minimizing overall compile time. The EDK IP components library is provided for VHDL only and may be encrypted. The Xilinx CompEDKLib utility deploys compiled models for EDK IP components into a common location. Unencrypted EDK IP components can be compiled using CompEDKLib. Precompiled libraries are provided for encrypted components.

Compiling everything

To find out how to compile all the libraries and all the IP blocks  for the IUS simulator we first read the
Embedded Systems Tools Guide. It tells us to use the Xilinx program compedklib to perform the compilation of all the libraries. We will use the program in GUI mode. Let's start. But before we start we will delete all old libraries we have compiled before. If not we may see a lot of compilation errors.

==> compedklib

Select the simulator to use.

Select directories to store compiled libraries.

Select directory to store EDK libs

Compile ISE and EDK libraries

Here is the result.

Now when we have everything compiled it is time to start building the complete simulation environment.That is the subject for the next chapter in this story.

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