New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, April 10, 2007
FPGA design from scratch. Part 16
IP creation overview

Any piece of IP you create must be compliant with the system that is in place. To ensure compliance, the following must occur:
  1. The interface required by your IP must be determined.
    The bus to which your custom peripheral will attach must be identified. For example:
    a. Processor Local Bus (PLB). The PLB provides a high-speed interface between the processor and high-performance peripherals.
    b. On-chip Peripheral Bus (OPB). The OPB allows processor access to low-speed, low-performance system resources.
  2. Functionality must be implemented and verified.
    Your custom functionality must be implemented and verified, with awareness that common functionality available from the EDK peripherals library can be reused. Your
    stand-alone core must be verified. Isolating the core ensures easier debug in the future.
  3. The IP must be imported to EDK.
    Your peripheral must be copied to an EDK-appropriate directory, and the Platform
    Specification Format (PSF) interface files (MPD and PAO) must be created, so other
    EDK tools can recognize your peripheral.
  4. Your peripheral must be added to the processor system created in XPS.
Create or import an user peripheral

One of the key advantages of building an embedded system in an FPGA is the ability to include customer IP and interface that IP to the processor. To start the Create and Import Peripheral Wizard select Hardware->Create or Import Peripheral.

Click the More Info button for more information. We will import an existing peripheral.

We will call our peripheral ETC (the name of the top module) and add a version to the name.

The peripheral is made up of Verilog files (.v).

We will use the ISE project file to define the Verilog source code.

Here are all the verilog source files.

The ETC peripheral will operate as an OPB slave (SOPB) and the OPB interface is already designed and verified. The
On-chip Peripheral Bus (OPB) is an IBM standard and is also used in the Power PC processor.

The wizard tries to map the ETC interface names to the standard naming convention for OPB. All the names that don't match have to be manually inserted.

It seems like we are missing some of the optional OPB signals. I have to add these signals to the top module
ETC.vI will add the missing pins and also some parameter statements defining register and memory address ranges. Like this:

parameter REGISTER_BASE_ADDR    = 32'h2000;
parameter REGISTER_HIGH_ADDR    = 32'h200c;
parameter MEM_BANK0_BASE_ADDR   = 32'h0;
parameter MEM_BANK0_HIGH_ADDR   = 32'hffc;
parameter MEM_BANK1_BASE_ADDR   = 32'h1000;
parameter MEM_BANK1_HIGH_ADDR   = 32'h1ffc;

In this window we have to select the right parameters defining the address range for registers and memory banks.

Here we define the interrupt signal and the operation of the interrupt.

Congratulations! We have added our peripheral to the current XPS project. Good work.

Here are all files in the pcores directory.

File description

XPS provides an interactive development environment that allows you to specify all aspects of your hardware platform. XPS maintains your hardware platform description in a high-level form, known as the Microprocessor Hardware Specification (MHS) file. The MHS, an editable text file, is the principal source file representing the hardware component of your embedded system. XPS synthesizes the MHS source file into Hardware Description Language (HDL) netlists ready for FPGA place and route.

The MHS File

The MHS file is integral to your design process. It contains all peripherals along with their parameters. The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture, peripherals, processor, connectivity, and address space. For more detailed information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter of the Platform Specification Format Reference Manual, available at

XPS Project Files

Here are more information about the
XPS project files used.

Xilinx IP center

There are many IP blocks available from Xilinx. Find out more in the
Xilinx IP center.

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Posted at 22:02 by

May 12, 2011   04:00 PM PDT
you r a such aworderful person
October 14, 2008   08:18 PM PDT
Thank you Sven!
I think this is the best blog I have acess.

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