New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Thursday, April 12, 2007
FPGA design from scratch. Part 17
Adding the ETC IP

The IP catalog tab shows all of the IPs that are available to use in an EDK project. To add the ETC IP:
  • Bring the IP catalog tab forward
  • Expand the Project Repository hierarchy
  • Drag and drop the ETC into the System Assembly View or double click on the ETC.
  • Expand the ETC instance
  • Highlite the slave OPB connection (SOPB)
  • Select the No Connection pull down menu and change it to mb_opb

Port connection

All OPB signals have already been connected to OPB bus. The remaining signals can be connected using the port view. We will make all signals external. Some input signals not used will be connected to ground and some unused output signals will be left unconnected.

Generate addresses

Select the Address filter to define addresses for the newly added ETC peripheral. The address can be assigned by entering the Base Address or the tool can assign an address. We will let the tool generate addresses:
  • Change the size of the memory blocks to 1K and for the register map to 4.
  • Click the Generate Addresses

A message in the console window will state that the address map has been generated successfully. The design is now ready to be implemented.

Mixed language design

All IP blocks from Xilinx are written in VHDL. The ETC IP is written in Verilog and therefor this design will be a mixed language design. The synthesis and simulation tools have no problems dealing with mixed language designs and hopefully this will not complicate our design job.

Set project options

Select Project->Project Options and click the HDL and Simulation tab. Because the majority of the design is in VHDL we will generate a VHDL top entity file. We will use NCSim for our simulations and we will allow mixed language behavioral files.

Generate the system netlist

We can now generate the system netlist. Click Hardware->Generate Netlist. The generation starts and returns with the following error message:

   line 43 - calculated index is out of signal VEC range of [0:3]

Completion time: 1.00 seconds

ERROR:MDT - platgen failed with errors!

*** [implementation/microblaze_0_wrapper.ngc] Error 2


Let's open the
ETC_v2_1_o.mpd file and figure out what the problem is. The OPB_BE signal is a four bit bus and not a one bit signal as I thought. If we add VEC [0:3] to the OPB_BE definition this problem will be fixed and we can rerun the netlist generation.

This is incredible. The whole netlist generation runs without any problems and it took less than 10 minutes on my MacBook using a virtual machine (Parallels Desktop) and Ubuntu Linux. Here is the
log file and here are all the warnings.

What happend during the netlist generation

When we start the netlist generation the following command is executed: platgen -p xc4vfx12ff668-10 -lang vhdl   ETC_system.mhs

                                                                                                 (Courtesy of Xilinx)

Hardware generation is accomplished with the Platform Generator (Platgen) tool. Platgen constructs the programmable system on a chip in the form of hardware netlists (HDL and implementation netlist files). Platgen creates a hardware platform using the Microprocessor Hardware Specification (MHS) file as input. In addition to netlist files in various formats such as NGC and EDIF, Platgen creates support files for downstream tools and top-level HDL wrappers to allow you to add other components to the automatically generated hardware platform. Read more about Platgen in the
Embedded Systems Tools Guide  (chapter 2).

During the Platgen run the following directories have been created and filled with files.
  • hdl
  • implementation
  • synthesis
The HDL directory contains all the HDL verilog and VHDL wrapper files that instantiates the IP blocks used in the design. The VHDL IPs always have VHDL wrappers and the Verilog IPs have Verilog wrappers. The top module ETC_system.vhd is a VHDL entity because we specified a VHDL netlist to be generated.

The implementation directory holds all the NGC files. The NGC file is a netlist that contains logical design data and constraints. This file replaces both EDIF and Netlist Constraints (NCF) files.

The synthesis directory holds all synthesis scripts used when running the syntesis tool XST.

We are now ready to program the FPGA on the evaluation board and start debugging the design. But before we do that we will setup a simulation environment and simulate the whole design. I am an old ASIC designer. Always simulate before implement.

Generate simulation HDL files

We will try the Xilinx HDL simulation environment. To generate the simulation setup goto the Simulation menu and select Generate Simulation HDL Files. The following script will start: make -f ETC_system.make simmodel. When the script has finished a new directory called simulation has been created.

Here is the
simgen log file.

Why simulate an embedded design
  • Using simulation, you don't have to wait for hardware to be complete before testing your software. The result: facilitated software development, which allows you meet more aggressive project deadlines.
  • Simulation provides insight into the internal workings of your system. Signals and register values are more accessible in a simulated system than they are once a design is in hardware.
  • Simulation also allows you complete control of your system. Conditions that may be difficult to create in a hardware setting are relatively easy to simulate.
Running a simulation in XPS

We will take these steps to start a simulation using NCSIM:
  1. cd /home/svenand/root/projects/ETC/xps/simulation/behavioral
  2. chmod 777 (make script executable)
  3. chmod 777
  4. Edit the file and change -lib_binding to -relax
  5. Start the simulation script: ./
Here are instructions from Xilinx on how to use NCSIM.

Read chapter 7 in the
EDK Concepts, Tools, and Techniques guide to find out more about simulating our design. Before we can start our simulation we need to write a simple software application that will run in our system. We will come back to simulation when we have finished this task.

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