New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


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and ask questions or make comments
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New Horizons
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Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
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A look at the equipment you need
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38000 feet above see level
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Photo Albums
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KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
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d9 Tech Blog
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EDA DesignLine
Eli's tech Blog
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Programmable Logic DesignLine
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Tuesday, April 17, 2007
FPGA design from scratch. Part 20
Running our first simulation

Our first testcase will be a simple one. We will start the system clock running at 100MHz. After a few clock cycles we will assert the system reset and watch what happens. Here is the

We are ready to start.
  • Testcase selected
  • Waveform generation enabled. Dump sst/wlf
  • NCSIM used
  • Compile/elaborate/simulate in one run selected

Here is the result.

The simulation stops after 110ns displaying the following error message: Input Error : RST on instance * must be asserted for 3 CLKIN clock cycles. It looks to me like the DCM  is missing a reset signal. Here starts the debugging phase. Up to now it has been "klipp och klistra" (Swedish for cut and glue) work. Now starts the real engineering work.
Let's open the Simvision waveform viewer
by clicking the Simvision button in the terminal window, find the dcm_0 and dcm_1 in the design browser, select all signals and open the waveform viewer.

The dcm_1 block has no input clock. Let's dig into the problem. We will use the Simvision Schematic Tracer to help us find our way around in the design. Here is a view of the complete system.

Here is the dcm_1 block in full view.

Here is the explanation, the ddr_feedback clock is missing. We have to add one more clock generator in our testbench.

    #DDR_CLK_ClockStart DDR_CLK_FB = 1;
    #DDR_CLK_ClockWidth DDR_CLK_FB = 0;

We will also add the DDR SDRAM to our simulation model.

Adding the DDR SDRAM

If we take a look at the Xilinx evaluation board we find two Micron DDR SDRAM 46V16M16 organized as 16Mx32. To download a Verilog model of this SDRAM we will go the
Micron web page.

Before we connect the DDR SDRAM to the ETC system we will study the SDRAM interface already implemented and try to understand how it works. Here is the Xilinx
document describing the interface. This table shows all the external signals in the DDR SDRAM interface.

 Signal  Width Dir
DDR_SDRAM_Clk_pin 1 Out
DDR_SDRAM_Clkn_pin 1 Out
Clock inverted
DDR_SDRAM_Addr_pin 0 : 12 Out
Address bus
DDR_SDRAM_BankAddr_pin 0 : 1 Out
Bank address
Active low column address strobe 
Clock enable
Active low chip select 
Active low row address strobe 
Active low write enable 
DDR_SDRAM_DM_pin 0 : 3  Out
Data mask 
DDR_SDRAM_DQS_pin 0 : 3  Inout
Data strobe both read and write
DDR_SDRAM_DQ_pin 0 : 31
Data bus in/out 

Here is an example showing the connection of two 16 bit DDR SDRAMS to the OPB DDR SDRAM controller.

(Courtesy of Xilinx)
Memory organization

OPB DDR SDRAM memory can be accessed as byte (8 bits), halfword (2 bytes), word (4 bytes) or Double word (8 bytes) depending on the size of the bus to which the processor is attached. From the point of view of the OPB, data is organized as
big-endian. The bit and byte labeling for the big-endian data types is shown below. To address 32 bit words the address must be incremented by 4 to read the next word. One more observation, the MSB is bit 0 and the LSB is bit 31, opposite to what you may be used to.

The DDR SDRAM Verilog model

Let's see if the Verilog model (ddr.v) matches the OPB interface. Here is the module declaration:
module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);  It seems we a perfect match.

Compilation of the Verilog DDR SDRAM module

We will compile the ddr.v file together with the include file ddr_parameters.vh to the database directory $ETC_VERIFICATION/database/ncsim/userlib/sdram_v1_00_a. The default memory compiled will have 16 bits data width and speed grade sg75Z. Fine for us.

Instantiation of two memory modules

Here is the instantiation that has been added to the EXT_system_testbench.tb.

/*                                                                       */
/*                 E X T E R N A L   C O M P O N E N T S                 */
/*                                                                       */

ddr    ddr_sdram_16_31    (

    .Clk                            (DDR_SDRAM_Clk_pin),
    .Clk_n                          (DDR_SDRAM_Clkn_pin),
    .Cs_n                           (DDR_SDRAM_CSn_pin),
    .Cke                            (DDR_SDRAM_CKE_pin),
    .Ba                             (DDR_SDRAM_BankAddr_pin),
    .Addr                           (DDR_SDRAM_Addr_pin),
    .Ras_n                          (DDR_SDRAM_RASn_pin),
    .Cas_n                          (DDR_SDRAM_CASn_pin),
    .We_n                           (DDR_SDRAM_WEn_pin),
    .Dm                             (DDR_SDRAM_DM_pin[2:3]),
    .Dqs                            (DDR_SDRAM_DQS_pin[2:3]),
    .Dq                             (DDR_SDRAM_DQ_pin[16:31]) );

ddr    ddr_sdram_0_15    (

    .Clk                            (DDR_SDRAM_Clk_pin),
    .Clk_n                          (DDR_SDRAM_Clkn_pin),
    .Cs_n                           (DDR_SDRAM_CSn_pin),
    .Cke                            (DDR_SDRAM_CKE_pin),
    .Ba                             (DDR_SDRAM_BankAddr_pin),
    .Addr                           (DDR_SDRAM_Addr_pin),
    .Ras_n                          (DDR_SDRAM_RASn_pin),
    .Cas_n                          (DDR_SDRAM_CASn_pin),
    .We_n                           (DDR_SDRAM_WEn_pin),
    .Dm                             (DDR_SDRAM_DM_pin[0:1]),
    .Dqs                            (DDR_SDRAM_DQS_pin[0:1]),
    .Dq                             (DDR_SDRAM_DQ_pin[0:15]) );

When we rerun our simulation the signals to the memory looks like this. Looks good to me.

If we run the simulation a little bit longer we get the following message.

ETC_SYSTEM_TEST.ddr_sdram_0_15: at time  202273 ns MEMORY:  Power Up and Initialization Sequence is complete
At time  202373 ns LMR  : Load Mode Register
At time  202373 ns LMR  : Burst Length = 2
At time  202373 ns LMR  : CAS Latency = 2

After the power up sequence is complete the auto refresh starts.

Suppressing assert messages in IEEE packages

When we have an 'x" in our simulation the VHDL packages will print millions of assert messages telling you there is an 'x' in your simulation. To suppress these message we can use the following tcl commands to ncsim:

ncsim> set pack_assert_off ieee.NUMERIC_STD
ncsim> set pack_assert_off ieee.STD_LOGIC_ARITH

We will add these commands to the TCL input file : $ETC_VERIFICATION/tcl/ncsim_tcl_input.def and they will be executed every time we run ncsim.

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