Entry: Zynq design from scratch. Part 46. Saturday, May 17, 2014

Adding push buttons and interrupts

This tutorial demonstrates how to modify our Zynq system from lab2 by adding inputs to the custom PL peripheral and connecting them to PS interrupts. This lab will show how to:

  • Modify the project's existing PS and PL subsystems
  • Update the C application for new hardware
  • Add interrupt handler and interrupt service routine (ISR)
  • Download and test the software application in hardware
1. We will use Vivado 2014.1 to build our new system.

--> vivado &

2. Open the LED_Controller project.

3. Expand system_wrapper in the Sources pane and double-click system_I -system (system.bd) to open Block Design. This is the new 2014.1 look.

4. Start to configure the AXI GPIO block by double-clicking the IP.

5. The Re-Customize IP window opens showing the AXI GPIO. Select the IP Configuration tab and check the setting for Enable Dual Channel. Set the GPIO 2 to All Inputs with GPIO Width 5. Check the setting for Enable Interrupt as well. Click OK.

6. Start to configure the PS block by double-clicking ZYNQ7 Processing System.

7. The Re-Customize IP window opens showing the ZYNQ Block Design.

8. We will start by adding a low speed clock (FCLK_CLK1) running at 250KHz and clocking the debounce circuit. Select Clock Configuration from the Page Navigator.

9. Before we can connect the interrupt signal we need to enable interrupts in the PS. Select Interrupts in the Page Navigator pane to the left and expand Fabric Interrupts and PL-PS Interrupt Ports. Enable Fabric Interrupts and IRQ_F2P[15:0]. Click OK.

10. Make a connection from ip2intc_irpt to IRQ_FP2[0:0] by holding down the left mouse button on one of the pins and draw a line to the other pin while still holding the button. The pointer should turn into a pen when the connection is made. A green check mark will show up at pins that are possible end points. Here is the connection made.

12. We also need to create external connections for the second GPIO channel that we can hook up to the rest of the logic in the PL. Right-click on the gpio2 interface symbol on the AXI GPIO block and select Make External. Select the gpio2 port symbol and rename the external interface from gpio2 to Pushbuttons in the External Interface Properties.

12. Here is the result.

13. Make the FCLK_CLK1 an external signal.

14. Improve the appearance by selecting Regenerate Layout and verify the connectivity by clicking Validate Design.

15. Save the Block Design by clicking Ctrl-S.

We have now added both an interrupt signal and an external port to the AXI GPIO. The interrupt signal has already been connected internally in the block design but the second gpio port is external to the block design. In the next part we will connect it to a HDL module.

Adding push buttons

We will modify and add HDL sources to connect the push buttons. When connecting pushbuttons, it is wise to debounce the signals. We will import a HDL module describing a debounce circuit circuit and connect the push buttons through it.

1. Since we have modified the block design we need to regenerate the HDL files that are required for implementation, simulation and synthesis. Expand Design Sources and system_wrapper (system_wrapper.v) in the Sources pane, right-click system(system.bd) and select Generate Output products. Click Generate.

2. Next we need to import the new HDL module that will debounce the pushbutton signals. We have already added a 250KHz clock from the PS that will be used to clock the debounce circuit and capture the pushbutton signals. The Verilog file debouncer.v can be downloaded from here (new version 2014-05-28).

3. To add the debouncer.v file to our design in the Flow Navigator pane select Project Manager->Add Sources.

4. Find and add the debouncer.v file.

5. Make sure that the box for Copy source into project is ticked and click Finish.

Modify the system_wrapper.v file

We need to modify the system_wrapper.v file to add our new debounce module. Double-click the system_wrapper.v file in the Design Source pane to open it in the Editor pane. We will make the following modifications:

  • Add an instantiation of the the debounce circuitry.
  • Add the FCLK_CLK1 signal
  • Connect clock, input and outputs to the rest of the system
  • Add a new input for the push buttons.
  • Connect debounce signals to the PROBE output
Save system_wrapper.v by typing ctrl-S. Here is the modified system_wrapper.v file (new version 2014-05-28).

RTL analysis

To get a graphical representation of our RTL code select RTL Analysis and click "Open Elaborated Design".

Synthesize the design

We need to clarify which external package pins that should be used to connect the input signals from the pushbuttons on the PCB. In order for Vivado to pick up all the signal names the design needs to be synthesized before I/O planning layout can be performed.

1. In the Flow Navigator pane, select Synthesis->Run Synthesis. The synthesis will take a few minutes to complete. Ignore any warnings. If we get an error we have to go back and check our design. Hopefully we get this message.

2. Change to Open Synthezised Design and click OK.

Connect package pins and implement the design

There are five push buttons connected to the PL. They are found here.

They are connected to the following package pins on the Zynq device.

3. Change to I/O planning layout in the toolbar. Follow the instructions in part 18 and add the five push buttons. Here is the result.

Generate bitstream

After fixing the package pins we are ready to generate a new bitstream file.

4. In the Flow Navigator pane, select Program and Debug->Generate Bitstream. Click Yes to run implementation. This will take a few minutes to complete. Ignore and close any warnings. When completed this window will be displayed.

5. Click OK to Open the Implemented Design. Must be open for exporting the bitstream file.

Export to SDK

6. Select File->Export->Export Hardware for SDK

Make sure to include the bitstream and click OK.

This completes the hardware session. In the next part we will add interrupt handling to our C application.

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February 3, 2015   09:45 AM PST

I've got a problem with the synthesis. When I run the synthesis the debouncer-block is removed ("is unused..."). I'm using a bit different debouncer design, implemented with VHDL. The schemantics shows only empty ports after the synthesis and the debouncer block is gone. In elaborated schema the debouncer shows up as it should.
August 20, 2014   06:34 PM PDT
I just wanted to update the comments on this page to say that the issue was reported and seems that it will be fixed in Vivado 2014.3.
July 18, 2014   05:48 PM PDT

Nice Contribution to beginners like me. I am having the same issue as "Ezra" posted below. I am also using ZC702
July 18, 2014   02:59 AM PDT
In 2014.2, choosing FCLK_CLK1 at 0.2 MHz causes Vivado to crash without giving any helpful error output during "Generate Output File". My project was on a ZC702.

I notice that the frequency range is given on the right, with 1 MHz as the minimum. Did you not have any issues with this during your design?
June 13, 2014   09:39 PM PDT
Hi Loic,

Make sure you have specified an I/O standard for every pin (not using the default settings). See picture above.
June 12, 2014   02:10 PM PDT
I have a problem when I generate the bitstream, here is the message : "[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 16 out of 159 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: PROBES[15:0]."
Do you have a solution please .

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